Several problems are associated with data transfer to and from VLSI and VHSIC chips and concern the large number of interconnections and their relatively low data rate. One bothersome limitation arises in that the transfer from the chips is limited in rate due to the large effective load capacitance on the output drivers, typically in the range of 30-50 picofarads. Generally speaking, in a conventional hardwire scheme each interconnection is dedicated to one bit of the digital word; parallel transmission on and from the chip usually is the rule. The effective load capacitance and vast number of parallel interconnections are interrelated since they both impact power consumption and the silicon area which must be dedicated to data transfer (in particular, transfer from the chip).
Off-chip data transmission from VLSI and VHSIC chips has serious limitations. Output buffers are needed to drive the capacitance of the bonding pads and wires attached to the chip carrier conductors. Charging this capacitive load, typically 30-50 picofarads, has required large MOS transistors, thus limiting speeds to about 10-megabits per second. Consequently, digital words are transmitted in parallel both on and off the chips as illustrated in FIG. 1. There are as many output pads as there are data nodes and each interconnection has an output buffer. This approach has resulted in a large number of output interconnections which reduces reliability, requires significant chip area and consumes 10-25% of the chip power budget. In addition since the VLSI and VHSIC devices operate at speeds greater by 10 or 100 times with respect to the reduced output data rates at the off-chip bottleneck, the chips are compromised further. This places significant limitations on systems architecture, particularly with regard to data formatting, partitioning and spatial distribution of computers. New developments in down scaling of devices will increase device speed and density, without affecting output buffer loading, thus exacerbating the off-chip data bottleneck.
Viewed from a different aspect, it can be said that the three root causes of the input and output limitations of conventionally designed VLSI and VHSIC chips can be gathered under the three designations of complexity-reliability, input-output speed and power dissipation.
Complexity and resultant reliability consequences have arisen with the increasing number of interconnections within more powerful digital systems. The number of interconnections is approximately proportional to the square root of the number of gates in the system. The reliability of a system is inversely proportional to the number of interconnections. These two factors have driven systems designers to VLSI and VHSIC; however, due to ever increasing system size, the total number of connections is still increasing so that there still is a decreasing of overall reliability.
This leads designers to consider that a desirable feature for any new technique for inputs and, particularly, outputs is a reduction of the number of connections. Reduction of the number of connections contributes toward a reduction in the area required to accommodate them. Area arrays on interconnected pins on 0.1" center and perimeter arrays (for example, leadless chip carriers with outputs on 0.03" centers) yield pin densities of approximately one hundred pins/in.sup.2. For a 50,000 gate system Rent's Rule predicts approximately 3,000 interconnected pins on thirty in.sup.2 of circuit board at one hundred pins/in.sup.2. This compares to the approximately 0.1 in.sup.2 of chip area. With the proper scaling the chip area will decrease and the present area ratio of 300:1 will exceed 1,000:1 illustrating the dominant role of interconnections in VLSI and VHSIC packaging.
The second root cause concerning the input-output speed of the integrated circuit affects the chip size. The driving force to scale down the size of integrated circuit devices is to increase the device speed. Several scaling schemes have been proposed, of which two that apply to MOS technologies, are the constant field scaling and constant voltage scaling. Considering only the zeroeth order effects and the general impact of device scaling, constant field scaling requires that all linear dimensions and voltages are reduced by some factor "S" while the channel doping is increased by the same factor. The inherent inverter delay decreases by S and internal electric fields and the power density remain constant. However drive current is reduced by a factor of S and operating voltages must be reduced. This leads to noise margin problems as kT does not change and crosstalk increases with speed. With constant voltage scaling linear dimensions are reduced by S, operating voltages remain constant and channel doping increases by S.sup.2. This scaling scheme causes the reduction of the propagation delay by S and the noise margin and saturation current are maintained with the power density increasing as S.sup.3. As a consequence, constant voltage scaling is precluded for all but special purpose functions.
The two scaling schemes just discussed result in an increased on-chip operating speed proportional to the scaling constant; however, the operating speed of a circuit is not necessarily limited by the inherent inverter delay; rather, it is presently limited by the time required to charge a capacitive load. The constant field scaling scheme calls for a reduction of both the voltage and the maximum drive current by the scaling factor S and, consequently, the switching speed of an inverter is proportional to the scaling of the load capacitance. This applies to both on-chip circuitry and output line drivers. In the on-chip case, the load capacitance is reduced by S and on-chip speed increases by S. For output drivers however, the load capacitance from subsequent inputs, packages, circuit boards, connectors, etc., is not reduced and off-chip speed would remain unaffected by device scaling. Therefore the development of lower capacitance input-output techniques are necessary to exploit VLSI and VHSIC chips.
The last root cause of problems associated with data transfer to and from VSLI and VHSIC chips is the power dissipation. For a silicon chip operating at room temperature, the maximum possible heat conduction through the silicon to the package is approximately 20-watts/cm.sup.2. However the maximum rate at which heat can be removed from the package by forced air cooling is less than 1-watt/cm.sup.2. Therefore, any air cooled system must provide a cooling area at least twenty times greater than the chip area if the chips are to be operated at their internal heat conduction limit. The foregoing analysis ignores other heat sources such as external resisters and power supplies which increase the heat load without increasing the number of gates in the system. For liquid cooled systems cooling rates up to 7-watts/cm.sup.2 have been reported. These liquid cooling systems are more applicable to fixed systems than to mobile systems. Typically 10-25% of the power consumed by VLSI or VHSIC are due to output buffers. Increased performance requirements for output buffers will increase this percentage and further aggravate the cooling problem. Any new output scheme must address the power consumption limitation.
Therefore, a continuing need exists in the state-of-the-art for an apparatus and method for improving the data transfer capabilities to and preferably from VLSI and VHSIC chips that avoids the root causes of input/output limitations as discussed hereinabove.